The conventional approach to buses in computer systems in which the same information was transmitted to, and received from, a plurality of system elements, such as CPUs, memories, or the like, was to use a multi-drop bus. A typical multi-drop bus consists of a number of bus wires that run to each element.
A beneficial aspect of a multi-drop bus is that only one bus element, such as a CPU, is allowed to transmit on the bus at a time and all bus elements can see what is being transmitted on the bus.
A drawback of the multi-drop bus is that all of the bus elements are always connected to the bus and the control of arbitration for access to the bus is predicated on separate communications between a bus element and other bus elements. This takes time and, therefore, slows down the processing speed of the system.
While multi-drop buses work well for many systems, as processing speeds increase, these bus systems have problems. These problems are a direct result of the plurality of bus elements being coupled to the same line.
In particular, devices based on ECL logic have experienced substantial problems with multi-drop bus systems. These problems have prevented such ECL based systems from operating at design speed. The result, therefore, was that in a high speed system, buses operated at a much slower speed that negated the processing speed advance endemic in these systems.
Hence, there is a need for a bus that can be used in a multiprocessor environment with a shared memory which operates at high speed, with logic such as ECL logic.